Relatively large amounts of storage is generally required in programmable logic circuits and to support programmable digital processor circuits. Accordingly, such needs for large amounts of storage has driven the design of capacitors suitable for digital data storage to extremely sophisticated levels and scaling to extremely small sizes such that many millions of such capacitors can be formed on a chip of reasonable size in dynamic random access memories (DRAMs) and relatively large amounts of storage can be formed on the same chip with relatively large amounts of logic circuitry such as is found in microprocessors.
Regardless of the structure in which such dynamic storage is formed, substantial amounts of logic is required to selectively access individual storage capacitors or groups of storage capacitors and to determine the charge stored on them. Generally, a transistor is formed at each of the storage capacitors and one conduction terminal connected to a conductor (e.g. bit line, BL) and the other conduction terminal connected to one plate or storage node of the storage capacitor. An individual capacitor connected to the conductor can be selected by energization of the control terminal of the transistor through a further conductor (e.g. word line, WL) that may also be connected to the corresponding control terminal of other transistors connected other word lines. The bit line can be connected to a data source for writing data to the storage node or a sense amplifier for reading stored data. The logic for connecting the bit lines to a data source or sense amplifier and selectively energizing the word lines and bit lines (usually involving an address decoder) is generally referred to as the support area of the memory which may also contain addition (e.g. processor) logic.
The storage capacitors which have one plate or storage node connected to a transistor, as discussed above will generally have the other plate connected in common with all of the other storage capacitors in the memory array or at least a given portion thereof, generally referred to as the array area of the memory, through the substrate. Therefore, it has been necessary to provide isolation between array areas of the chip forming a common connection to the storage capacitors and the portion of the chip forming the support area of the memory.
In the past, such isolation was formed as a deep trench-like recess enclosing the support area of the chip and was referred to as a moat while storage capacitors were formed in recesses extending for a lesser distance into the substrate. Therefore, the recesses for the moat and for the storage capacitors had substantially different topology and isolation could be provided by the moat even if the structure inside the moat was similar to that within the storage capacitors since the capacitor dielectric could be applied directly to the semiconductor material surrounding moat as well as the capacitor recesses. The semiconductor material would thus form a capacitor plate as well as provide electrical insulation on the interior of the moat. Such a structure provided both convenience and economy since processing to form capacitors included processes which were common to the moat.
However, in an effort to provide improved characteristics and performance of the capacitors, metal-insulator-metal (MIM) capacitor designs have recently been introduced in which metal is first deposited on the interior surface of the capacitor recesses, followed by an insulator (preferably a high dielectric constant or “Hi-K” material) and a further metal layer and metal and/or semiconductor material fill. The first metal in certain cases can be made to react with the semiconductor substrate to form semiconductor-metal alloys such as silicides. When these layers are formed within a recess having a high depth to width aspect ratio, the layers will be very thin due to reduced flux of material precursors due to tight geometry in high aspect ratio structures and increased capacitance can be achieved from the small separation of metal plates across an extremely thin insulator that is preferably a high dielectric constant (Hi-K) material (e.g. having a dielectric constant above about eight).
If the metal applied to the interior of the capacitor recesses is also applied to the interior of the moat, however, the isolation function would be defeated since current can flow through the metal on the bottom of the moat recess. The alternative of full decoupling of the formation of the capacitor and moat formation is expensive and presents at least a problem of close overlay error tolerance which can compromise manufacturing yield.